Ball grid array (BGA) semiconductor packages are mainstream package products in the light of providing a sufficient amount of I/O (input/output) connections for use with semiconductor chips that incorporate high density of electronic elements and electronic circuits. As such a highly-integrated chip operates to consequently produce relatively more heat, it is thereby important to promptly remove the heat from the chip; otherwise, heat accumulation in the chip would undesirably damage electrical performances and reliability of package products. Moreover, for protecting internal components of the semiconductor package against external contamination, it usually forms an encapsulant that encapsulates the chip and other conductive elements such as bonding wires. The encapsulant is made of a resin material with poor thermal conductivity (coefficient of thermal conductivity around 0.8w/m°K); therefore, the chip-generated heat would not be efficiently dissipated to the atmosphere through the encapsulant; this would thereby adversely affect performances and lifetime of the chip by virtue of heat accumulation.
In response to the above heat-dissipation, problem, there is adopted a heat dissipating structure in the BGA semiconductor package for facilitating dissipation of heat generated from the chip. However, this heat dissipating structure is embedded in the encapsulant, such that the chip-generated heat still needs to pass through the encapsulant for dissipation. Therefore, this structural arrangement cannot achieve satisfactory improvement in heat dissipating efficiency for the semiconductor package.
Accordingly, U.S. Pat. No. 5,977,626 discloses a semiconductor package with a heat dissipating structure being partly exposed to the atmosphere and also directly contacting with a chip. As shown in FIGS. 5 and 6, in this semiconductor package 3, a heat dissipating structure 33 is provided on a substrate 30 above a chip 31 mounted on the substrate 30. The heat dissipating structure 33 comprises: a flat portion 330 having a top face 330a exposed to outside of an encapsulant 34 that encapsulates the chip 31 and bonding wires 32 that electrically connect the chip 31 to the substrate 30; and a single encircled support portion 331 peripherally situated at the flat portion 330 and extending downwardly from a bottom surface 330b of the flat portion 330 to be attached to the substrate 30, wherein the flat portion 330 and the encircled support portion 331 integrate to form a receiving space 35 where internal components such as the chip 31, bonding wires 32 and passive components (not shown) are placed. The encircled support portion 331 is integrally formed with a laterally-extending contact portion 332 at a bottom position thereof, and the contact portion 332 may be provided with a plurality of protruding portions 333 respectively extending downwardly to be attached to the substrate 30. Moreover, on the bottom surface 330b of the flat portion 330 there is formed a protrusion 334 extending to abut against an active surface 310 of the chip 31. This allows heat generated by the chip 31 during operation to be transmitted through the protrusion 334 to the exposed top face 330a of the flat portion 330 by which the heat can be dissipated to the atmosphere, so as to provide excellent heat dissipating efficiency for the semiconductor package 3.
However, the above semiconductor package 3 has significant drawbacks. In compliance with low profile packaging technology and high integration of chip development, substrates are preferred to be down-sized nearly to chip scale, and incorporated with sufficient conductive elements such as bonding wires required for accommodating highly-integrated chips with densely-arranged electronic elements or circuits. As a result, the above heat dissipating structure 33 is considered to occupy too much space on the substrate 30 in a manner that, the receiving space 35 embraced by the flat portion 330 and the single encircled support portion 331 with integrally-formed contact portion 332, makes all internal components of the semiconductor package 3 position-restrictedly enclosed in the receiving space 35. Thereby, the bonding wires 32, passive components or other electronic components (not shown) can only be disposed on the substrate 30 at area within coverage of the heat dissipating structure 33 in the receiving space 35. This drawback makes the semiconductor package 3 with the heat dissipating structure 33 hardly applied for accommodating highly-integrated chips that require a large amount of active and passive components as well as conductive elements to be comfortable situated on the substrate 30 for achieving desirable operational and electrical performances.
Further due to the heat dissipating structure 33 being located outside area for incorporating electronic components on the substrate 30, in another aspect, the substrate 30 may need to be increasingly sized in order to dispose a sufficient number of active and passive components as well as conductive elements on the substrate 30; this would make the substrate 30 considerably larger in size than the chip 31, thereby unfavorable to profile miniaturization.